1. Field of the Invention
The present invention relates to semiconductor memory devices and data paths using the same. More particularly, the present invention relates to a semiconductor memory device such as a multiport memory capable of writing data simultaneously from a multiport (i.e., multiple ports) into an array of memory cells or reading the data therefrom, and a data path using such a multiport memory.
2. Description of the Prior Art
FIG. 25 is a block diagram showing memory cells of a conventional multiport memory of a 4-word.times.4-bit configuration as well as peripheral circuits thereof.
Referring to FIG. 25, the memory cells 1 store data therein and those memory cells are arrayed in four rows and four columns to constitute a memory cell array. Address decoders 2a and 2b are provided to address each memory cell 1. The address decoder 2a receives write address signals WA0 and WA1 and output terminals of the address decoder 2a are connected with write word lines WW0 to WW3. The write word lines WW0 to WW3 are connected to the corresponding memory cells 1 arrayed in the row direction.
The address decoder 2b receives bit address signals RA0 and RA1 and it has output terminals connected to read word lines RW0 to RW3. Those read word lines RW0 to RW3 are connected to the corresponding memory cells 1 arrayed in the row direction. The memory cells 1 arrayed in the column direction are connected to write bit lines WB0 to WB3 and read bit lines RB0 to RB3. The write bit lines WB0 to WB3 are connected to output terminals of write circuits 30 to 33, and input terminals of the write circuits 30 to 33 receive data DI.sub.0 to DI.sub.3. The read bit lines RB0 to RB3 are connected to input terminals of sense amplifiers 40 to 43, which output read data DO.sub.0 to DO.sub.3.
The write address signals WA0 and WA1, the write word lines WW0 to WW3, the write bit lines WB0 to WB3, the address decoder 2a and the write circuits 30 to 33 constitute write ports, while the read address signals RA0 and RA1, the read word lines RW0 to RW3, the read bit lines RB0 to RB3, the address decoder 2b and the sense amplifiers 40 to 43 constitute read ports.
FIG. 26 is an electric circuit diagram of a memory cell shown in FIG. 25.
Referring to FIG. 26, inverters 5a and 5b have a cross connection of input and output terminals A and B, to constitute a flip-flop, the terminal A being connected to a write bit line WB through an access gate 6 formed by an N channel MOS transistor. The access gate 6 has a gate connected to a write word line WW. The terminal B is connected to a transmission inverter 7, which has an output terminal C connected to a read bit line RB through an access gate 8 formed by an N channel MOS transistor. The access gate 8 has a gate connected to a read word line RW. As can be seen from FIG. 26, only one write bit line WB is connected for one port of each memory cell 1.
FIG. 27 is an electric circuit diagram showing an example of a write circuit. In FIG. 27, the write circuit 30 comprises two inverters 30a and 30b connected in series. The other write circuits 31 to 33 are formed in the same manner as in the write circuit 30.
FIG. 28 is an electric circuit diagram showing an example of a sense amplifier. In FIG. 28, the sense amplifier 40 comprises two inverters 40b and 40c connected in series and it has an input pull-up gate 40a connected on the input side of the inverter 40b. The other sense amplifiers 41 to 43 are formed in the same manner as in the sense amplifier 40.
FIG. 29 shows another example of a sense amplifier, which is a current sense type.
Referring now to FIGS. 25 to 29, write operation of the conventional multiport memory will be described. The data DI.sub.0 to DI.sub.3 to be written are supplied to the write circuits 30 to 33. The write circuits 30 to 33 set the write bit lines WB0 to WB3 to "1" or "0" according to the data DI.sub.0 to DI.sub.3. Words to be written out of the four words of the memory cell array are addressed by the write address signals WA0 and WA1. More specifically, the address decoder 2a decodes the write address signals WA0 and WA1 and sets any one of the write word lines WW0 to WW3 to "1" and the other three lines to "0" in response to the write address signals WA0 and WA1. The access gate 6 of the memory cell 1 connected to the write word line WW at "1" is conducted, whereby the write bit line WB and the terminal A are electrically connected. A sum of an output resistance of the write circuits 30 and an on resistance of the access gate 6 is set lower than an output resistance of the inverter 5b. Thus, when the access gate 6 is conducted, the value of the terminal B becomes equal to that of the write bit line WB designated by the data DI irrespective of the initial values of the terminals A and B. In consequence, the data is written.
When the write word line WW is set to "0", the write bit line WB and the terminal A are electrically disconnected and the values of the terminals A and B immediately before the change of the write word line WW from "1" to "0" are maintained by the flip-flop including the inverters 5a and 5b. Accordingly, due to the action of the address decoder 2a, correct data is not written in the memory cell 1 connected to the write word line WW set to "0".
Next, data read operation will be described. Reading of data in the multiport memory is performed by means of the read ports. More specifically, words to be read out of the four words are designated by the read address signals RA0 and RA1. The address decoder 2b decodes the read address signals RA0 and RA1 and sets only any one of the read word lines RW0 to RW3 to "1" and the other three lines to "0" according to the combination of those read address signals RA0 and RA1. The access gate 8 of the memory cell 1 connected to the read word line RW set to "1" is conducted, whereby the value of the terminal B is inverted by the transmission inverter 7 and the access gate 8, to set the read bit line RB at the value of the terminal A.
The values of the read bit lines RB0 to RB3 are detected and amplified by the sense amplifiers 40 to 43 and those amplified values are outputted as the data DO.sub.0 to DO.sub.3. Since an input impedance viewed from the side of the terminal B of the transmission inverter 7 is extremely high, the initial value of each read bit line RB is never transmitted to the corresponding terminal B through the corresponding terminal C. Accordingly, the values of the terminals A and B maintained in the flip-flop including the inverters 5a and 5b are never inverted by read operation.
Since the conventional multiport memory is thus constructed, when a write word line WW is set to "1", data are written in all the memory cells 1 of the corresponding row in the memory cell array. Therefore, it is necessary to establish a one-to-one correspondence between one row and one word and between one column and one bit. In consequence, a proportion of the memory cell array cannot be set freely and a distance between a write circuit and a sense amplifier located corresponding to one bit is narrow, which involves difficulties in layout and causes an increase in an area of the device because of increase of the height of the device. In addition, in a multiport memory having a large number of words, a bit line length is increased which involves disadvantages such as increases in delay time and charge and discharge currents.